This invention relates to a digital PLL (phase-locked loop) circuit.
A digital PLL circuit divides a master clock signal having a frequency equal to N (integral number) times the frequency of an input signal (clock signal) normally by N, compares the phases of the division output signal and the input signal with each other, and divides the input signal so that the phases of them may coincide with each other (for example, by temporarily varying the dividing ratio N) to synchronize the division output signal with the input signal.
An exemplary one of conventional digital PLL circuits is shown in FIG. 6. Referring to FIG. 6, the conventional digital PLL circuit shown includes a fixed oscillator 41 which oscillates a master clock signal of a frequency of 15.36 MHz which is equal to 192 times the frequency of 80 kHz of an input signal.
The digital PLL circuit further includes a divider (frequency divider) 42 which divides the master clock signal from the fixed oscillator 41. The dividing ratio of the divider 42 is variable between 191 and 193.
The digital PLL circuit further includes a phase comparator 43 which compares the input signal in phase with the output of the divider 42.
In operation, the master clock signal of the frequency of 15.36 MHz generated by the fixed oscillator 41 is divided by 191 or 193 by the divider 42. The phase comparator 43 compares the phases of the input signal and the output of the divider 42 with each other, and when the phase of the output of the divider 42 lags with respect to that of the input signal, the phase comparator 43 controls the divider 42 so that the dividing ratio of the divider 42 may be 191 (refer to the waveforms (a) to (c) in FIG. 7). On the contrary, when the phase of the output of the divider 42 leads with respect to that of the input signal, the phase comparator 43 controls the divider 42 so that the dividing ratio of the divider 42 may be 193 (refer to the waveforms (a) to (c) of FIG. 8).
FIG. 9 shows another exemplary one of conventional digital PLL circuits. Referring to FIG. 9, the conventional digital PLL circuit shown includes a fixed oscillator 41 and a phase comparator 43 similar to those of the conventional digital PLL circuit shown in FIG: 6. The conventional digital PLL circuit further includes a random walk filter (RWF) 71 having a function of an integrating circuit and thus having a function of suppressing a jitter or error components.
The digital PLL circuit further includes a divider (frequency divider) 72 which divides a master clock signal from the fixed oscillator 41 and has a dividing ratio which is variable among 191, 192 and 193.
It is assumed here that the initial value of the random walk filter 71 is 0 and the dividing ratio of the divider 72 is 192.
In operation, when the phase comparator 43 determines that the output of the divider 72 leads in phase to the input signal, the random walk filter 71 decrements its value by one, but on the contrary when the phase comparator 43 determines that the output of the divider 72 lags in phase with respect to the input signal, the random walk filter 71 increments its value by one. When the value of the random walk filter 71 becomes equal to an integration time constant thereof on the positive side as a result of repetition of the operations just described, the dividing ratio of the divider 72 is varied to 191 and the value of the random walk filter 71 is cleared to 0. On the contrary when the value of the random walk filter 71 becomes equal to its integration time constant on the negative side, the dividing ratio of the divider 72 is varied to 193 and the value of the random walk filter 71 is cleared to 0.
It is to be noted that, when the value of the random walk filter 71 does not overflow, that is, in any other case than those cases described just above (that is, when the absolute value of the value of the random walk filter 71 is smaller than the integration time constant), the dividing ratio of the divider 72 is maintained at 192.
When the input signal has some jitter or some error component and it is desired to suppress the jitter of the output signal, such a digital PLL circuit including a random walk filter as the conventional digital PLL circuit shown in FIG. 9 is employed commonly. In this instance, when it is desired to enhance the jitter suppressing effect, the integration time constant of the random walk filter 71 is increased. However, when the frequency error of the master clock signal is great, the magnitude of the integration time constant is limited. This is because, while the amount by which the phase can be controlled once by the divider 72 must be greater than the amount of displacement in phase by a frequency error, if the integration time constant is increased, then the interval in which phase control is performed becomes long and the phase is displaced by the frequency error during the interval.
In particular, where the input frequency is represented by f.sub.in, the dividing ratio by N, the frequency of the master clock signal by f.sub.m, and the integration time constant by MOF, then when f.sub.in &gt;f.sub.m /N, EQU ((1/f.sub.in)-(1/f.sub.m /N)).times.MOF&lt;1/f.sub.m
but when f.sub.in &gt;f.sub.m /N, EQU ((1/(f.sub.m /N))-(1/f.sub.in)).times.MOF&lt;1/f.sub.m
In other words, when f.sub.in &gt;f.sub.m /N, MOF&lt;(f.sub.in /(f.sub.in .times.N-f.sub.m), but when f.sub.in &lt;f.sub.m /N, MOF&lt;(f.sub.in /f.sub.m -f.sub.in .times.N)).
Therefore, since normally a maximum frequency error is provided as a characteristic of an oscillator used for a supply source of a master clock signal, the random walk filter 71 is designed with an integration time constant calculated in accordance with the equation above based on the maximum value.
However, in such a conventional digital PLL circuit as described above, since the integration time constant of the random walk filter is fixed, normally the random walk filter is designed with an integration time constant which can be calculated using a maximum frequency error provided as a characteristic of an oscillator used as a supplying source of a master clock signal. However, since the maximum frequency error provided as a characteristic of an oscillator commonly includes initial fluctuation, temperature variation, secular variation and so forth, an ordinary frequency error is smaller in most cases than the maximum frequency error, and the interval after which phase control is performed becomes excessively short. Consequently, there is a tendency that phase control is performed excessively frequently and the jitter width likely becomes large.